Tokuzo Kiyohara

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A compiler for VLIW and superscalar processors must expose sufficient instruction-level parallelism (ILP) to effectively utilize the parallel hardware. However, ILP within basic blocks is extremely limited for control-intensive programs. We have developed a set of techniques for exploiting ILP across basic block boundaries. These techniques are based on a(More)
Compilers for superscalar and VLIW processors must expose su cient instruction-level parallelism in order to achieve high performance. Compiletime code transformations which expose instruction-level parallelism typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to(More)
Code optimization and scheduling for superscalar and superpipelined processors often increase the register requirement of programs. For existing instruction sets with a small to moderate number of registers, this increased register requirement can be a factor that limits the effectivess of the compiler. In this paper, we introduce a new architectural method(More)
By exploiting fine grain parallelism, superscalar processors can potentially increase the performance of future supercomputers. However, supercomputers typically have a long access delay to their first level memory which can severely restrict the performance of superscalar processors. Compilers attempt to move load instructions far enough ahead to hide this(More)
with Limited Register Files Tokuzo Kiyohara John C. Gyllenhaal Media Research Laboratory Coordinated Science Laboratory Matsushita Electric Industrial Co., Ltd. University of Illinois, Urbana-Champaign Kadoma-shi, Osaka, 571 Japan Urbana, IL 61801 Abstract Moderate size register les can limit the performance of loop unrolling on multiple issue processors.(More)
By exploiting ne grain parallelism, superscalar processors can potentially increase the performance of future super-computers. However, supercomputers typically have a long access delay to their rst level memory which can severely restrict the performance of superscalar processors. Compilers attempt to move load instructions far enough ahead to hide this(More)
Graphical interfaces and windowing systems are now the norm for computer-human interaction. Also, advances in computer networking have given computer users access to immense distributed resources accessible from anywhere on the network. In this setting, the desktop, or personal, computer plays the role of a user-interface engine that mediates access to the(More)
By exploiting ne grain parallelism, superscalar processors can potentially increase the performance of future super-computers. However, supercomputers typically have a long access delay to their rst level memory which can severely restrict the performance of superscalar processors. Compilers attempt to move load instructions far enough ahead to hide this(More)
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