Tiong Aik Koh

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
A memory-based, pipelined, serial architecture is developed for implementing product accumulate codes in field programmable gate arrays. A three-stage pipeline structure is exploited on the min-sum decoding algorithm to achieve full utilization of instantiated resources, to reduce latency, and to increase throughput while keeping the performance degradation(More)
  • 1