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—A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors, and three 16 KB shared memories; and is implemented in 65 nm CMOS. All processors and shared memories are clocked by local fully independent,(More)
Modern applications increasingly require the computation of DSP workloads comprised of a variety of numerically-intensive DSP tasks. These workloads are found in communication, multime-dia, embedded, and wireless applications, and often require very high levels of computation and high energy efficiency. The Asynchronous Array of Simple Processors (AsAP)(More)
—A low-complexity message-passing algorithm, called Split-Row Threshold, is used to implement low-density parity-check (LDPC) decoders with reduced layout routing congestion. Five LDPC decoders that are compatible with the 10GBASE-T standard are implemented using MinSum Normalized and MinSum Split-Row Threshold algorithms. All decoders are built using a(More)
—This paper presents a low power platform which performs continuous multi-channel detection and analysis of seizures for epilepsy patients. The detection unit, upon detecting a seizure, enables an analysis circuit that locally processes and transmits energy and frequency contents of the EEG data. Transmission traffic reduction of 256x is achieved by locally(More)
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and significantly simplifies row processors— which results in smaller area,(More)