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We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR),(More)
In RPL the pair wise metric may result in a single node with good transmission quality, linked to many neighboring nodes which are associated with a large number of children nodes. In this case, for one DODAG the parent node can be severely congested which results in a large number of packets drop due to buffer limitation on the parent node side. We propose(More)
Due to the resource-constraint features of LLNs and inherent vulnerabilities of RPL, the security design of deploying Intrusion Detection and Prevention System (IDPS) is widely used. However, IDPS has large energy consumption which is a major concern of LLNs. In order to protect LLNs and save energy resources, we propose an energy-efficient IDPS scheme(More)
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