Ting-Jung Lin

  • Citations Per Year
Learn More
Prior work has shown that due to the overhead incurred in enabling reconfigurability, field-programmable gate arrays (FPGAs) require 21× more silicon area, 3× larger delay, and 10× more dynamic power consumption compared with application-specific integrated circuits (ASICs). We have earlier presented a hybrid CMOS/nanotechnology(More)
We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic reconfiguration is done intra-circuit rather than(More)
Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration(More)
The precise GPS high-low tracking data from the joint Taiwan-USA mission FORMOSAT-3/COSMIC (COSMIC) can be used for gravity recovery. The current orbital accuracy of COSMIC kinematic orbit is 2 cm and is better than 1 cm for 60-s normal points. We model the perturbing forces acting on the COSMIC spacecraft based on standard models of orbit dynamics. The(More)
Intellectual Properties (IPs) mapping algorithms for On-Chip-Networks (OCNs) allocate a set of IPs onto given network topologies. The existing mapping algorithms limit a single IP to connect to a single router. Hence, the IPs with large communication volumes will result in heavy traffic loads of certain routers. Those routers may become hot spots due to(More)
  • 1