Learn More
A memory-efficient architecture design for de-blocking filter in H.264/AVC is presented. We use the novel data arrangement of Column-of-Pixel to facilitate the memory access and reuse the pixel value. Further, we propose a hybrid filter scheduling to improve the system throughput. As compared with some existing approaches of realizing de-blocking filter [1](More)
Motion compensation is always the main bottleneck in real-time or high quality video applications; thus, fast and efficient motion compensation is necessary. In this paper, a new motion compensation design is presented to overcome large calculation time of complicated motion vector prediction (MVP) algorithm and high motion resolution in H.264/AVC. By(More)
We design, implement, and evaluate an H.264/SVC decoder and an HTTP video streaming client on multi-core mobile devices. The decoder employs multiple decoder threads to leverage the multi-core CPUs, and the streaming server/client support adaptive HTTP video streaming. To evaluate the decoder performance, we conduct experiments using real H.264/SVC videos(More)
—A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865µW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on(More)
A single-chip MPEG-2 SP@ML and H.264/AVC BL@L4 video decoder is fabricated in a 0.18µm 1P6M CMOS technology with an area of 15.21mm 2. This chip contains 19.2kb and 3.55kb of embedded SRAM for storing neighboring pixels and control tags, and adopts two 4MB SDRAMs for further system integration. It operates at a power-level that is about one order of(More)
In this paper, we propose a 4x4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders [1][2], which adopt macroblock level pipelines, our proposed 4x4-block level pipelining architecture of H.264/AVC decoder achieves better hardware(More)
Today's mobile Internet is heavily overloaded by the increasing demand and capability of mobile devices, in particular, multimedia traffic. However, not all traffic is created equal, and a large portion of multimedia contents on the mobile Internet is delay tolerant. We study the problem of capitalizing the content transfer opportunities under better(More)
A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18?m CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps(More)