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In this paper, we present a novel fully adaptive and fault-tolerant routing algorithm for Network-on-Chips (NoCs) called Force-Directed Wormhole Routing (FDWR). The proposed routing algorithm is implemented in the switches of a TLM (Transaction Level Model) packet switching NoC using SystemC. Based on these switches, mesh, torus, and hypercube topologies(More)
UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative performance analysis is not adequately taken into account in early design stages of the system. In this paper, we present our approach for formal and simulation based performance(More)
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architec-tures, that enables architecture exploration and optimization. The automated generation of Network-on-Chip architectures covers beside the generation of the communication infrastructure, the automated integration of IP-components. The automated(More)
Many advanced driver assistance systems (ADAS) and autonomous vehicles require 3D information available from (stereo) camera systems. The corresponding task of estimating disparity or optical flow is computationally demanding, so meeting real-time update rates at high image resolutions has proven to be challenging. Modern parallel hardware seems suitable(More)
In this paper, we present a novel approach for automated mapping of software processes onto the cores of MPSoC architectures using a regular packet-based communication infrastructure. During the mapping determination, the communication distance as well as the routing algorithm for packet-based communication are taken into account. The basic idea of the(More)
In this paper, we present a novel approach for automated latency-optimized mapping of processes onto cores of NoC-based MPSoCs. During the mapping determination, the routing algorithm for packet-based communication is taken into account. The basic idea of the presented approach is the reduction of communication conflicts on the communication network links(More)
In this paper we present a demonstrator for an advanced driver assistance system using stereo perception, consisting of two Leutron Vision CheckSight cameras, a Tilera TILExpressPro-64 board with a TILEPro64 embedded multicore processor as image processor.
In this paper we present a novel approach for mapping interconnected software components onto cores of homogenous MPSoC architectures. The analytic mapping process considers shared memory communication as well as the routing algorithm controlling packet-based communication. The software components are mapped with the constraints of avoiding communication(More)
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