Tim R. LaRocca

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A 57-65 GHz differential and transformer-coupled power amplifier using a commercial 90 nm digital CMOS process is presented. On-chip transformers combine bias, stability and input/interstage matching networks for a compact design with an area of 0.15 mm<sup>2</sup>. The three-stage amplifier consumes 70 mA under 1.2 V supply voltage. The small-signal gain(More)
Digital control of the effective dielectric constant of a differential mode transmission line is shown up to 60GHz in standard CMOS technology. The effective dielectric constant is shown to increase from 5 to over 50 for the fixed artificial dielectric case. The digital controlled artificial dielectric transmission line (DiCAD) uses MOS switches to(More)
A new injection-locked frequency divider (ILFD) circuit topology, by combining the strengths of LC type ILFD (LC_ILFD) and ring oscillator type ILFD (RO_ILFD), is proposed to achieve high speed, low power, wide locking range and accurate quadrature output phases. The frequency-division criterion is analyzed and agrees well with simulation results. The(More)
A digital controlled artificial dielectric (DiCAD) differential transmission line is embedded in 90nm CMOS to digitally tune a 58-64GHz DCO. DiCAD varies εr,eff from 18.8 to 32.5. A shunt open stub DiCAD provides discrete capacitive tuning with 13.1 S11 phase variation. The core oscillator is an inductively loaded differential, cross-coupled NMOS pair.(More)
A digitally controlled artificial dielectric (DiCAD) differential transmission line is designed to perform agile linear phase shift over 100&#x00B0; with thermometer-coded 16step control. It also operates with a 16 gain-step VGA to enable re-configurable and direct-frequency modulation at 60GHz with 256<sup>2</sup> states (1.1&#x00B0; angular and 0.0007(More)
A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ(More)
A 94GHz 64QAM 1Gbps reconfigurable system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) and back-etched thru silicon waveguide power combiners is presented. The SoC includes a 7M gate ASIC with reconfigurable digital modulation and transmit pre-coding. The ASIC feeds two 10b 1.4GHz current-steering DACs followed by a direct(More)
The first dynamic 4-bit, digitally-assisted GaN high power amplifier (DAPA) system transmitting 7.68Msymbol/s with 64-QAM modulation is presented. An FPGA is programmed to generate the pulse-shaped 64-QAM signal, perform envelope estimation, and time-align the RF and digital control signals arriving at the DAPA. A high-speed, level-shifting circuit converts(More)