The XPIC by Scott Frederick Masch This thesis describes a fast high level design flow and design of a Microchip PIC compatible micro controller. The design executes in RAM and uses a four stage pipeline for high performance and indeed achieves substantially better performance than any comparable micro controller in comparable technology.
We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit, or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of… (More)