Tim Callahan

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In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically reconfigurable datapath (e.g. an FPGA), and a memory hierarchy. We have developed a framework called Nimble that automatically compiles system-level applications specified in C to(More)
The Garp project [3] quantitatively investigates the benefits of adding an on-chip dynamically reconfigurable coprocessor to a standard instruction processor. Intended for acceleration of loops, Garp’s coprocessor performs iteration control and both streaming and random memory accesses without assistance from the instruction processor. The companion project(More)
Preface In the past two decades, the fields of VLSI systems design and massively parallel computation have grown into mature disciplines. Both fields began as research topics in industrial and academic laboratories; today, they form the core technologies for several large corporations. This report proposes a massively parallel computer, the Connectionist(More)
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