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This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8 10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput.(More)
A packet-switched 6 4 2-D mesh network providing 2 Tb/s of bisectional bandwidth with a per-hop latency of 4-cycles, forms the high performance communication fabric for a Single-Chip Cloud Computer (SCC) with 48 PentiumTM class IA-32 cores. The fabric operates on an independent power supply and frequency domain. The router micro-architecture achieves over(More)
Floating point multiply-accumulate (FPMAC) unitis the backbone of modern processors and is a key circuit determining the frequency, power and area of microprocessors. FPMAC unit is used extensively in contemporary client microprocessors, further proliferated with ISA support for instructions like AVX and SSE and also extensively used in server processors(More)
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