Tianzhou Chen

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STT-RAM has emerged as one of the most promising candidates for future on-chip cache due to STT-RAM's high density and low leakage. However, the STT-RAM has many disadvantages, such as: high write energy and long writing latency. To alleviate the problems, many STT-RAM and SRAM hybrid cache architectures have been proposed. In this paper, we propose a(More)
Dept. of Elec. and Comp. Engr., University of Kentucky, Lexington, KY 40506, USA College of Comp. Sci. and Software Engr., Shenzhen University, Shenzhen, GD 518060, China Dept. of Elec. and Comp. Engr., Florida International University, Miami, FL 33174, USA Dept. of Comp. Sci. and Software Engr., Auburn University, Auburn, AL 36849, USA College of Comp.(More)
Along with the mobile Internet growing up, mobile terminal device are becoming more and more multiplicity and the application development are become more difficult. In this paper, we propose a cross-platform application development environment supported by cloud service. This development environment abstract hardware capability makes developers needn't(More)
With the development of Graphics Processing Unit (GPU) and the Compute Unified Device Architecture (CUDA) platform, researchers shift their attentions to general-purpose computing applications with GPU. In this paper, we present a novel parallel approach to run artificial fish swarm algorithm (AFSA) on GPU. Experiments are conducted by running AFSA both on(More)
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of <i>less reused lines</i> that are never reused or reused for few times. In this case, the cache performance can be improved through retaining a portion of working set in cache for a period long(More)
The wide application of embedded systems becomes a trend in the post-PC era. Embedded systems have been deployed in numerous fields which have different requirements of embedded systems architecture. In order to&#x0A0;&#x0A0;adapt to the needs of different fields, this paper proposes a new course model for embedded system education. This course model(More)
In heterogeneous multi-core systems, the scheduling overhead increases as the number of processor cores increasing. To improve the scheduling efficiency, a hardware scheduler is designed to assist the task scheduling for synergistic core in heterogeneous multi-core architecture in this paper, which support first come first served (FCFS) and dynamic priority(More)
Multiple heterogeneous processor systems on chip are more and more widely used in order to provide a higher system performance. Run-time mapping for heterogeneous Network on Chip (NoC) is challenging since the sequence of the incoming applications is unknown in advance. This paper presents Heterogeneous Near Convex Region Algorithm (HNCR), an incremental(More)
As the scaling of integration, massive remote communication has become the main bottleneck of system performance for network-on-chip (NoC). Most packets have to travel long distances from source to destination, leading to long latency and severe contention. Hybrid Wireless NoC(HWiNoC) has emerged as a popular method to handle remote transmission in NoC, in(More)