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In 3D-IC technology, electromigration (EM) degradation has become severe due to the high thermal-mechanical stress induced by the Through-Silicon-Vias (TSVs). However, little has been done on designing an EM-robust clock tree for 3D-ICs. In this paper, we propose a systematic EM-aware clock tree synthesis design flow, to enhance the 3D clock tree's EM(More)
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D integration technology emerges as a viable option to improve chip performance and increase device density in a direction orthogonal to costly device scaling. As 3D integration is becoming a promising technology for next-generation chip design, recent years have(More)
This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSV’s EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSV’s EM is mutually influenced by neighboring TSVs (due to TSV EM’s(More)
This paper presents a post-placement technique for through-silicon-via (TSV) induced thermal mechanical stress reduction. Thermal mechanical stress causes several critical failures such as material fracture (interfacial delamination and silicon substrate cracking) and TSV stress migration (SM). The von Mises stress is used as a material fracture metric. An(More)
Three-dimensional integration enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to(More)
We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique(More)