Tiantao Lu

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Three-dimensional integration enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to(More)
In 3D-IC technology, electromigration (EM) degradation has become severe due to the high thermal-mechanical stress induced by the Through-Silicon-Vias (TSVs). However, little has been done on designing an EM-robust clock tree for 3D-ICs. In this paper, we propose a systematic EM-aware clock tree synthesis design flow, to enhance the 3D clock tree's EM(More)
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