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DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning
TLDR
We show that it is possible to design an accelerator with a high throughput, capable of performing 452 GOP/s (key NN operations such as synaptic weight multiplications and neurons outputs additions) in a small footprint of 3.02 mm2 and 485 mW. Expand
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Cambricon-X: An accelerator for sparse neural networks
TLDR
We propose a novel accelerator, Cambricon-X, to exploit the sparsity and irregularity of NN models for increased efficiency. Expand
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PuDianNao: A Polyvalent Machine Learning Accelerator
TLDR
We present an ML accelerator called PuDianNao, which accommodates seven representative ML techniques, including k-means, k-nearest neighbors, naive bayes, support vector machine, linear regression, classification tree, and deep neural network. Expand
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Linear Time Memory Consistency Verification
TLDR
This paper proposes the first linear-time software-based approach to memory consistency verification with pending period information. Expand
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DianNao family
TLDR
In this article, we introduce a series of hardware accelerators (i.e., the DianNao family) designed for ML (especially neural networks), with a special emphasis on the impact of memory on accelerator design, performance, and energy. Expand
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LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging
TLDR
We propose a novel scheme, named LDet, to determinize a chip through removing the nondeterminism in transfers crossing different clock domains, even when these clock domains are heterochronous. Expand
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