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During their biogenesis, 40S ribosomal subunit precursors are exported from the nucleus to the cytoplasm, where final maturation occurs. In this study, we show that the protein kinase human Rio2 (hRio2) is part of a late 40S preribosomal particle in human cells. Using a novel 40S biogenesis and export assay, we analyzed the contribution of hRio2 to late 40S(More)
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficient performance evaluation methods are of highest importance for a broad search in the solution space. In this paper we present an approach that captures the SoC functionality for(More)
The assembly of ribosomal subunits in eukaryotes is a complex, multistep process so far mostly studied in yeast. In S. cerevisiae, more than 200 factors including ribosomal proteins and trans-acting factors are required for the ordered assembly of 40S and 60S ribosomal subunits. To date, only few human homologs of these yeast ribosome synthesis factors have(More)
—This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The(More)
Manycore System-on-Chip include an increasing amount of processing elements and have become an important research topic for improvements of both hardware and software. While research can be conducted using system simulators, prototyping requires a variety of components and is very time consuming. With the Open Tiled Manycore System-on-Chip (OpTiMSoC) we aim(More)
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via(More)
Ethernet, although initially conceived as a Local Area Network technology, has been steadily making inroads into access and core networks. This has led to a need for higher link speeds, which are now reaching 100 Gbit/s. Packet processing at this rate represents a significant challenge, that needs to be met efficiently, while minimizing power consumption(More)