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—By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host processor itself. With direct access to the host processor's(More)
In this paper we present an implementation of the image compression routine SPIHT in reconfigurable logic. A discussion on why adaptive logic is required, as opposed to an ASIC, is provided along with background material on the image compression algorithm. We analyzed several Discrete Wavelet Transform architectures and selected the folded DWT design. In(More)
In this work, we present a survey of the different task scheduling parallel programming models in order to support Out-of-Order (OoO) execution for high performance computing in an Multiprocessor System on Chip (MPSoC) environment. Thus, we review different parallel programming approaches, as well as current heterogeneous parallel programming models. In(More)
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