some Windows display setups may be source of corrupted Mastar graphics. If this is the case, we advise to • setup standard fonts in the Properties/Appearance window (available with the right-button click on the desktop Windows screen) • adjust the screen resolution to 1024x768 pixels or more in the Properties/Settings window (available with the right-button… (More)
SUMMARY Experimental investigations on detection of terahertz radiation are presented. We used plasma wave instability phenomenon in nanometer Silicon field effect transistor. A 30 nm gate length transistor was illuminated by THz radiation at room temperature. We observe a maximum signal near to the threshold voltage. This result clearly demonstrates the… (More)
This paper surveys a few of the emerging bioMEMS technologies at EPFL for improved, inexpensive health care. The lab-on-a-chip systems use dielectrophoretic forces to direct cell movement within microfluidic networks and impedance spectroscopy for label-free inflow characterization of living cells. The implantable microelectrodes for neural applications are… (More)
Intrinsic parameter fluctuations steadily increase with CMOS technology scaling. Around the 65 nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Device mismatch due to intrinsic parameter fluctuation causes each memory cell of the millions in a typical memory array to have… (More)
In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I<sub>OFF</sub> (< 20 pA/mum) and high I<sub>ON</sub> (> 2.2… (More)
The continuous scaling down of SiO/sub 2/ gate oxide is bound to reach its physical limits owing to gate leakage and reliability concerns. High-k dielectrics have been identified to replace the conventional SiO/sub 2/ as gate dielectrics materials. One of the main concerns which could be show-stopper for a successful integration of these new materials is… (More)