Thomas Skotnicki

Learn More
This paper investigates terahertz detectors fabricated in a low-cost 130 nm silicon CMOS technology. We show that the detectors consisting of a nMOS field effect transistor as rectifying element and an integrated bow-tie coupling antenna achieve a record responsivity above 5 kV/W and a noise equivalent power below 10 pW/Hz(0.5) in the important atmospheric(More)
A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guarantied by epitaxial process. The SON process allows the buried dielectric (which may be an oxide but also an air gap) to be(More)
Experimental investigations on detection of terahertz radiation are presented. We used plasma wave instability phenomenon in nanometer Silicon field effect transistor. A 30 nm gate length transistor was illuminated by THz radiation at room temperature. We observe a maximum signal near to the threshold voltage. This result clearly demonstrates the(More)
This paper surveys a few of the emerging bioMEMS technologies at EPFL for improved, inexpensive health care. The lab-on-a-chip systems use dielectrophoretic forces to direct cell movement within microfluidic networks and impedance spectroscopy for label-free inflow characterization of living cells. The implantable microelectrodes for neural applications are(More)
The continuous scaling down of SiO/sub 2/ gate oxide is bound to reach its physical limits owing to gate leakage and reliability concerns. High-k dielectrics have been identified to replace the conventional SiO/sub 2/ as gate dielectrics materials. One of the main concerns which could be show-stopper for a successful integration of these new materials is(More)
Intrinsic parameter fluctuations steadily increase with CMOS technology scaling. Around the 65 nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Device mismatch due to intrinsic parameter fluctuation causes each memory cell of the millions in a typical memory array to have(More)
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I<sub>OFF</sub> (&lt; 20 pA/mum) and high I<sub>ON</sub> (&gt; 2.2(More)
A compact model for the threshold voltage in DoubleGate MOSFET is developed. The model takes into account short-channel effects, carrier quantization and temperature dependence of the threshold voltage. We assume a parabolic variation of the potential with the vertical position in the silicon film at threshold. An analytical expression for the surface(More)