Learn More
Category: B Intended for publication in the formal proceedings. All appropriate clearances for the publication of this paper have been obtained, and if accepted the author will prepare the final manuscript in time for inclusion in the Conference Proceedings and will present the paper at the conference. Summary VIS (Verification Interacting with Synthesis)(More)
We present heuristic algorithms for finding a minimum BDD size cover of an incompletely specified function, assuming the variable ordering is fixed. In some algorithms based on BDDs, incompletely specified functions arise forwhich any cover of the functionwill suffice. Choosing a cover that has a small BDD representation may yield significant performance(More)
Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with(More)
Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms for the approximation and decomposition of BDDs. In this paper we present a new algorithm for approximation(More)
Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedra-based Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we(More)
We present <i>Ketchum,</i> a tool that was developed to improve the productivity of simulation-based functional verification by providing two capabilities: (1) <i>automatic test generation</i> and (2) <i>unreachability analysis.</i> Given a set of "interesting" signals in the design under test (<i>DUT</i>), automatic test generation creates input stimuli(More)
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now gaining acceptance in advanced design groups. This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a(More)