#### Filter Results:

- Full text PDF available (20)

#### Publication Year

1989

2012

- This year (0)
- Last 5 years (1)
- Last 10 years (2)

#### Publication Type

#### Co-author

#### Journals and Conferences

#### Key Phrases

Learn More

- Robert K. Brayton, Gary D. Hachtel, +13 authors Tiziano Villa
- CAV
- 1996

ion Manual abstraction can be performed by giving a file containing the names of variables to abstract. For each variable appearing in the file, a new primary input node is created to drive all the nodes that were previously driven by the variable. Abstracting a net effectively allows it to take any value in its range, at every clock cycle. Fair CTL model… (More)

- Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
- 31st Design Automation Conference
- 1994

We present heuristic algorithms for finding a minimum BDD size cover of an incompletely specified function, assuming the variable ordering is fixed. In some algorithms based on BDDs, incompletely specified functions arise forwhich any cover of the functionwill suffice. Choosing a cover that has a small BDD representation may yield significant performance… (More)

- Thomas R. Shiple, Gérard Berry, Hervé J. Touati
- ED&TC
- 1996

Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with… (More)

- James H. Kukula, Thomas R. Shiple
- CAV
- 2000

Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms for the approximation and decomposition of BDDs. In this paper we present a new algorithm for approximation… (More)

- Pei-Hsin Ho, Thomas R. Shiple, +5 authors Jiang Long
- ICCAD
- 2000

We present <i>Ketchum,</i> a tool that was developed to improve the productivity of simulation-based functional verification by providing two capabilities: (1) <i>automatic test generation</i> and (2) <i>unreachability analysis.</i> Given a set of "interesting" signals in the design under test (<i>DUT</i>), automatic test generation creates input stimuli… (More)

Implicit state enumeration for extended finite state machines relies on a decision procedure for Presburger arithmetic. We compare the performance of two Presburger packages, the automata-based Shasta package and the polyhedrabased Omega package. While the raw speed of each of these two packages can be superior to the other by a factor of 50 or more, we… (More)

- Adnan Aziz, Felice Balarin, +10 authors Alberto L. Sangiovanni-Vincentelli
- 31st Design Automation Conference
- 1994

Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now gaining acceptance in advanced design groups. This has been facilitated by the use of binary decision diagrams (BDDs). This paper describes the essential features of HSIS, a… (More)

- Michael Mendler, Thomas R. Shiple, Gérard Berry
- Formal Methods in System Design
- 2012

- In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley
- FMCAD
- 2002

We describe a new method to simplify combinational circuits while preserving the set of all possible values (that is, the range) on the outputs. This method is performed iteratively and on the fly while building BDDs of the circuits. The method is composed of three steps; 1) identifying a cut in the circuit, 2) identifying a group of nets within the cut, 3)… (More)