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A novel VLSI architecture for binary multipliers is introduced. It is based on an existing parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. The VLSI implementation of the proposed parameterized binary multiplier architecture (PBMA) is obtained by applying this(More)
A novel VLSI array architecture for vector-scalar multiplication is introduced. It is based on a parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. Two variations of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), namely PVSMA-A and(More)
A computationally efficient mismatched filter comprised of a matched filter in cascade with a multi-stage filter based on v is proposed. For this approach to work, the autocorrelation of the given code has to satisfy certain conditions that are derived in this work. If in addition, the sidelobes are sparse and of small integer values, such as in Barker(More)
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