Register renaming is often used to improve performance in many high-ILP processors. However, there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.
In this paper, we present a detailed analysis of the Me-diaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia. Me-diaBench performance characteristics were examined by running Medi-aBench under the SimpleScalar simulation environment. Characteristics such as instruction mix, branch… (More)
— Interactive deformable object modeling is important for a number of application areas. Unfortunately, computational complexity quickly grows beyond the capabilities of consumer systems as model detail increases. Our first contribution is to analyze this application, and present details that might aid in optimizing existing algorithms or in developing new… (More)
In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms and their architectural implementation (SPARTA), which is specifically tuned for real-time use. We expect performance orders of magnitude higher than general-purpose CPUs.
Physical modeling of a mass-spring system allows for realistic object motion and deformation in a virtual environment. Previous work in this type of physical modeling relies on general-purpose hardware, and cannot offer the performance necessary for real-time human-machine interaction. In this paper, we consider the co-design of software and hardware in… (More)