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—We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posyn-omial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of(More)
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a geometric program, a special type of convex optimization(More)
Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of(More)
We present an efficient method for optimal design and synthesis of CMOS inductors for use in RF circuits. This method uses the the physical dimensions of the inductor as the design parameters and handles a variety of specifications including fixed value of inductance, minimum self-resonant frequency, minimum quality factor, etc. Geometric constraints that(More)
OBJECTIVE Problems involving drug knowledge are one of the most common causes of serious medication errors. Although the information that clinicians need is often available somewhere, retrieving it expeditiously has been problematic. At the same time, clinicians are faced with an ever-expanding pharmacology knowledge base. Recently, point-of-care technology(More)
We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as <italic>posynomial</italic> functions of the design variables. As a result, the LC oscillator design problems can be posed as a <italic>geometric program</italic>, a special type of(More)
A 1.4-GHz LC voltage-controlled oscillator has been implemented in a MOSIS 0.5-&#181;m CMOS process. Complementary cross-coupled PMOS and NMOS transistors enhance single-ended symmetry at each of the resonant nodes, reducing close-in phase noise. Tapped bond wires provide a resonant tank with high Q. At an offset frequency of 100 kHz, the measured phase(More)
Experimental verification of noise models is one of the major challenges in noise modeling. A circuit-based noise characterization technique is introduced which uses phase noise measurement data to extract MOSFET noise parameters. After a brief discussion on MOSFET noise, experimental data is presented on the severity of excess noise in a 0.18 µm CMOS(More)