Thomas Chiarella

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We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show(More)
Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeplyscaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded(More)
In this paper we demonstrate superior NBTI reliability of SiGe pFETs with ultra-thin EOT in a Replacement Metal Gate (RMG) process flow, and in a SiGe channel bulk pFinFET architecture. Moreover, we investigate the Forward Body Bias (FBB) technique showing that it can very efficiently improve the SiGe device ION without compromising the NBTI reliability, or(More)
Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure of the random component of time-dependent variability. We show that it can be extracted using matched pairs, analogously to time-zero variability. To that end, the defect-centric statistics of(More)
The mechanism responsible for the short-channel electron mobility (e<sup>$</sup>mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N <sub>t</sub>)(More)
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and(More)
Abstract: Bias temperature instabilities (BTI) are serious reliability issues in high-k technologies and occur for positive and negative stress voltages in both n and pMOSFETs. The cases with the strongest degradation, namely negative BTI (NBTI) in pMOS and positive BTI (PBTI) in nMOSFETs, are typically studied and modeled separately, which led to(More)