Thomas Chiarella

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The mechanism responsible for the short-channel electron mobility (e<sup>$</sup>mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N <sub>t</sub>)(More)
In this paper we demonstrate superior NBTI reliability of SiGe pFETs with ultra-thin EOT in a Replacement Metal Gate (RMG) process flow, and in a SiGe channel bulk pFinFET architecture. Moreover, we investigate the Forward Body Bias (FBB) technique showing that it can very efficiently improve the SiGe device I ON without compromising the NBTI reliability,(More)
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and(More)
The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET). After post-deposition annealing (PDA) and SF6 plasma treatment, the hole mobility is improved. From low-frequency noise analysis, reduction of the trap density and noise level is observed in PDA- and(More)
The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni<sub>3</sub>Si<sub>2</sub> at the FUSI/dielectric interface(More)