Thomas C. Hartrum

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Distributing computation among multiple processors is one approach to reducing simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors of the circuit among the available processors in order to obtain maximum speedup. A complicating factor that is often(More)
Over the past several years, the Air Force Institute of Technology (AFIT) has been developing a formal-based software synthesis system, the AFIT Wide Spectrum Object Modeling Environment (AWSOME), along with a speci cation language AWL (AFIT Wide-spectrum Language). Several tools have been developed, including a parser for the AWL syntax, an interactive(More)
Parallel Logic Simulation of Digital Circuits By Hong Kyu Kim Parallel discrete event simulation (PDES) is e cient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments(More)
ÐFormal software specification has long been touted as a way to increase the quality and reliability of software; however, it remains an intricate, manually intensive activity. An alternative to using formal specifications directly is to translate graphically based, semiformal specifications into formal specifications. However, before this translation can(More)