Thomas C. Hartrum

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Distributing computation among multiple processors is one approach to reducing simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors of the circuit among the available processors in order to obtain maximum speedup. A complicating factor that is often(More)
Formal software speciication has long been touted as a way to increase the quality and reliability of software; however, it remains an intricate, manually intensive activity. An alternative to using formal speciications directly is to translate graphically-based, semi-formal speciications into formal speciications. However, before this translation can take(More)
We present a conservative strategy for spatially decomposed parallel discrete event battlefield simulation. The traditional null message algorithm provides a foundation from which a mapping to generic simulation attributes can be made. We informally discuss preservation of logical correctness and freedom from deadlock. Experimental results demonstrate the(More)
Parallel discrete event simulation (PDES) is eecient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments were performed to demonstrate that the two proposed(More)