Thomas Boden

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Network processors are programmable, highly integrated communications circuits optimized to provide processing at high data and packet rates. The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors,(More)
This 40 Gb/s network processor has a dataflow architecture with 200 PISC/spl trade/ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 /spl mu/m CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.
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