Thilo Maurer

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Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this(More)
Recently the latest generation of Blue Gene machines became available. In this paper we introduce general metrics to characterize the performance of applications and apply it to a diverse set of applications running on Blue Gene/Q. The applications range from regular, floating-point bound to irregular event-simulator like types. We argue that the proposed(More)
With POWER8 a new generation of POWER processors became available. This architecture features a moderate number of cores, each of which expose a high amount of instruction-level as well as thread-level parallelism. The high-performance processing capabilities are integrated with a rich memory hierarchy providing high bandwidth through a large set of memory(More)
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