Theodore Sabety

  • Citations Per Year
Learn More
In this paper, we describe an experimental prototype VLSI chip that was designed to serve as the basis for a massively parallel supercomputer called NON-VON 3. The chip, which is implemented in 3-micron nMOS technology, contains eight S-bit processing elements (PE’s), each embodying 64 bytes of static RAM. Significant features of the design include: an(More)
This paper describes a recently implemented program that very rapidly generates control paths for different variants of the constituent processing elements of a particular massively parallel machine; the NON-VON Supercomputer. The program, called PLATO, accepts as input a set of instruction opcodes, together with associated control information, and produces(More)
Today there are many tools available that automatically produce IC layouts; however, designers are reluctant to accept the results produced by these programs. This session will explore the underlying assumptions and basic algorithms used in the design and development of these systems and will introduce the approach of the Jedi Designer system. The(More)
  • 1