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Design specific variation in pattern transfer by via/contact etch process: full-chip analysis
A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable of
Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis
A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/contact etch (VCE) processes. This physics-based algorithm is
Anisotropic Inter-Poly Dielectric technology for conventional floating gate type flash memory
Anisotropic Inter-Poly Dielectric (AIS IPD) has been successfully developed. It enables center SiN thickness to be thicker at Floating-Gate (FG) top and thinner at FG side. Using AIS IPD, both
The Generation of Hot Carriers in a Semiconductor Rod with a Notch
The current transport mechanism of the SOGICON-type Ge device is studied. Current-voltage characteristics were measured by applying pulsed voltage. As the voltage was increased, there appeared first
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation
A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable to