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This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard cells and the proposed method automatically creates yield-enhanced cell layouts by de-compacting the original cell layout. However, the careless modification of the original layout(More)
This paper proposes an exact cell layout synthesis technique to minimize the probability of wiring faults due to spot defects. We modeled the probability of faults on intra-cell routings with considering the spot defects size distribution and the end effect of critical areas. By using the model as a cost function, we comprehensively generate the minimum(More)
This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes the high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum width cells with routability under our layout styles. It considers(More)
We introduce a 4<sup>2</sup>x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18&mu;m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than(More)
Transgenic silkworms can be useful for investigating the functions of genes in the post-genomic era. However, the common method of using a transposon as an insertion tool may result in the random integration of a foreign gene into the genome and suffer from a strong position effect. To overcome these problems, it is necessary to develop a site-specific(More)
This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. We formulate the transistor placement problem into Boolean Satisfiability (SAT)(More)