Tetsuya Iizuka

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To construct an efficient system for the production of recombinant proteins in silkworm (Bombyx mori), we investigated the promoter activity of the silkworm sericin 1, 2, and 3 genes (Ser1, Ser2, and Ser3) using a GAL4/UAS binary gene expression system in transgenic silkworm. The promoter activity of the upstream region of Ser1 was strong, yielding high(More)
The transport pathway of specific dietary carotenoids from the midgut lumen to the silk gland in the silkworm, Bombyx mori, is a model system for selective carotenoid transport because several genetic mutants with defects in parts of this pathway have been identified that manifest altered cocoon pigmentation. In the wild-type silkworm, which has both genes,(More)
Transgenic silkworms can be useful for investigating the functions of genes in the post-genomic era. However, the common method of using a transposon as an insertion tool may result in the random integration of a foreign gene into the genome and suffer from a strong position effect. To overcome these problems, it is necessary to develop a site-specific(More)
A binary gene expression system using the yeast GAL4 DNA-binding protein and the upstream activating sequence (UAS) of galactose-driven yeast genes is an established and powerful tool for the analysis of gene function. However, in the domesticated silkworm, Bombyx mori, this system has been limited in its utility by the relatively low transcriptional(More)
The white, scarlet and brown genes of Drosophila melanogaster encode three half-type ATP-binding cassette (ABC) transporters. In Drosophila, precursors of ommochromes and pteridines are transported by White/Scarlet and White/Brown heterodimers, respectively. The white egg 2 (w-2) mutant of the silkworm, Bombyx mori, has white eggs and eyes because of lack(More)
This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes the high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum width cells with routability under our layout styles. It considers(More)
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard cells and the proposed method automatically creates yield-enhanced cell layouts by de-compacting the original cell layout. However, the careless modification of the original layout(More)