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Invited Paper The reliability issues of Flash electrically erasable pro-grammable read-only memory (Flash EEPROM) are reviewed in this paper. The reduction of the memory cell size and improvement in the reliability have been realized by several breakthroughs in the device technology; in particular, the reliability of the ETOX and NAND structure EEPROM will(More)
Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS(More)
A perpendicular magnetic-tunnel-junction (MTJ)-based 2T-2R ternary content-addressable memory (TCAM) cell is proposed for a high-density nonvolatile word-parallel/bit-serial TCAM. The use of MOS/MTJ-hybrid logic makes it possible to implement a compact nonvolatile TCAM cell with 2.5 &#x03BC;m<sup>2</sup> of a cell size in a 0.14-&#x03BC;m CMOS and a 100-nm(More)
A proposed linear regulator uses a Flexible Control technique of Output Current (FCOC) to achieve 96.5% efficiency. The FCOC technique realizes to drive a flexible output current according to the output current variation and stable output voltage supply. The linear regulator fabricated by 1.2um CMOS process occupies 0.423mm 2. The fabricated linear(More)