A multi-layered perceptron neural network with backpropagation algorithm (MLP/BP) is realized as a waveform equalizer for distorted nonreturn-to-zero (NRZ) data recovery in band-limited channels. Moreover, the proposed approach can tolerate sampling clock skew and channel response variance. According to simulation results, the proposed design can recover… (More)
A 2.4GHz low noise amplifier has been designed in a standard CMOS 0.35 urn process. The transistor model is Bsim3 for 0.35um process. The amplifier provides a forward gain of 33dB with a noise figure only 0.92dB while drawing 17mw from a 1.5 V supply. Design simulation results are presented in this paper.
This paper presents a multi-input multi-output (MIMO) multi-layered perceptron neural network with backpropagation algorithm (MLP/BP). The proposal is a waveform equalizer for distorted nonreturn-to-zero (NRZ) data recovery in band-limited channels with co-channel interference (CCI). From the simulation results, we note that the proposed design can recover… (More)
CMOS LC oscillators using high-Q active inductors with constant-power consumption are presented. The active inductor with one feedback resistor results in a gain-boosting factor to improve the Q-value and the inductance (L) of the active inductor. Based on this high-Q active inductor, a negative resistance LC-tuned oscillator with low constant-power… (More)
In this work, we base on generalized multi-layered perceptron neural networks with backpropagation algorithm (generalized MLP/BP) to construct multi-input multi-output (MIMO) decision feedback equalizers (DFEs). The proposal is used to recover distorted nonreturn-to-zero (NRZ) data in wireline parallel band-limited channels. From the simulations, we note… (More)
Abstraci-A dynamic ADC sampling methodology based on error-tracking loop is proposed in this paper to improve synchronized performance in DSSS baseband transceivers. To maintain the synchronized performance the ADC sampling rate is controlled by error-tracking loop to let clock offset becomes lower. For 1.8MHz clock offset based on 44MHz ADC sampling rate… (More)