Teresa Farris

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Total ionizing dose (>1 Mrad(Si)) and SEE test results at two commercial foundries for a 0.25 /spl mu/m radhard-by-design ASIC are reported in this paper. Radhard-by-design techniques provide denser, faster and lower power space applications.
Radhard-by-design has been advanced by embedding EDAC into a 16Mbit SRAM to harden the SRAM against single event upset. Conventional radhard-by-design techniques are used for the non-memory circuitry. The estimated uncorrectable double bit error rate is 2.9 times 10<sup>-16 </sup> errors/bit-day assuming a geosynchronous orbit, the Adam's 90% worst case(More)
A RadHard-by-design, PLL-based, single chip, clock network and clock generator solution has been designed, manufactured and tested. Hardness test results for the Aeroflex Colorado Springs RadClock/spl trade/ clock generator circuit designed for harsh space environment applications are presented.
Aeroflex's RadHard-by-Design commercially fabricated field programmable gate array provides a radiation hardened quick-turn solution to aerospace IC users. Characterization results for single event upset, single event latchup and total ionizing dose are presented.
A predictive SET event frequency model is used to describe the SET performance at any operating condition of a next generation PLL with 189,440 combinations of operating conditions. A DOE approach and 24 cross-section versus LET curves are used to model the large operating space of this PLL.