Tejas M. Bhatt

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We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when(More)
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the re-configurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check-node units (CNU) is predetermined and(More)
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation. We show that integrating Matlab with HDL design tools such as HDL designer® and Precision-C® , an efficient design flow, suitable(More)
In this paper, we evaluate the performance of the receiver employing an iterative RLS-based data detection and channel estimation for the structured irregular LDPC coded MIMO-OFDM system. Using the EXIT chart analysis, the performance of the detector with various approximate decoding algorithms is analyzed
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