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Previous anatomical studies have been unsuccessful in demonstrating significant cortical inputs to cholinergic and somatostatinergic striatal interneurons in rats. On the other hand, electrophysiological studies have shown that cortical stimulation induces monosynaptic EPSPs in cholinergic interneurons. It has been proposed that the negative anatomical(More)
The muscarinic acetylcholine receptor (mAChR) molecular subtype, m2, has been postulated to be the presynaptic cholinergic autoreceptor in many brain regions. However, due to a lack of subtype-specific pharmacological agents, conclusive evidence for m2 as an autoreceptor remains elusive. The development of subtype-specific antibodies has enabled extensive(More)
—This paper describes an approach to building Grid applications based on the premise that users who wish to access and run these applications prefer to do so without becoming experts on Grid technology. We describe an application architecture based on wrapping user applications and application workflows as web services and web service resources. These(More)
Gastrin/cholecystokinin-like immunoreactivity (G/CCK-LI) was localized by immunocytochemistry in neurons in the central nervous system of Aplysia californica. Neuronal cell bodies were specifically immunostained in the buccal, cerebral, pedal, and abdominal ganglia but not in the pleural ganglia. Neural G/CCK-LI processes were observed in the neuropil of(More)
—Embedded systems require low overhead security approaches to ensure that they are protected from attacks. In this paper, we propose a hardware-based approach to secure the operation of an embedded processor instruction-by-instruction, where deviations from expected program behavior are detected within the execution of an instruction. These security-enabled(More)
—We present a customizable soft architecture which allows for the execution of GPGPU code on an FPGA without the need to recompile the design. Issues related to scaling the overlay architecture to multiple GPGPU multiprocessors are considered along with application-class architectural optimizations. The overlay architecture is optimized for FPGA(More)
In this paper, we describe the use of magnetic RAM (MRAM) in coarse-grained reconfigurable arrays (CGRAs) as a configuration cache to allow for bulk low-energy storage and rapid device reconfiguration. If an energy-saving configuration update for an application is needed, a new configuration can be quickly swapped into compute blocks and interconnect(More)
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