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Recent interest in CMOS voltage scaling has produced a class of cache architectures which tolerate parametric SRAM failures at low voltage by substituting faulty words of one cache line with healthy words of another line. These caches rely on the fault maps (which grow reciprocally with smaller word sizes) for fault identification. Therefore, the benefits(More)
BACKGROUND The hypothesis of this study is that working on the simulator without a structured feedback does not change performance; hence, any effects shown after structured feedback would amount to useful learning of the procedure. The aim was to investigate the learning curve for the HT Immersion Medical Colonoscopy Simulator without any structured(More)
BACKGROUND The aim of this study was to investigate the relation between clinical experience and performance with regard to colonoscopic procedures performed on the HT Immersion Medical Colonoscopy Simulator. The hypothesis is that the performance of novice, intermediate, and experienced operators is different on simulators, just as it is on real patients.(More)
Voltage scaling can be applied to cache memories to reduce their energy consumptions. However, reduced supply voltage to the cache memories increases defective SRAM cells due to process variations, which will decrease their yields and performance nullifying the benefits of voltage scaling. To mitigate this problem, we propose a fault buffer-based scheme for(More)
Continuous scaling in CMOS fabrication process makes circuits more vulnerable to process variations, which results in variable delay, malfunctioning, and/or leaky circuits. Caches are one of the biggest victims of process variations due to their large sizes and minimal cell features. To mitigate the impacts of process variations on caches, we propose to(More)
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