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A new parallel computer, ADENART (previously it was called ADENA,) for numerical applications has been developed. It is composed of 256 processing elements (:PEs) and interconnection networtcHXnet.) Each PE consists of a dedicated floating-point processor VLSI whose sustained performance is 10 MFLOPS, a communication controller VLSI and locally-distributed(More)
This paper reports NAS Parallel Benchmark results on parallel machine ADENART, which has been developed through collaboration between Kyoto University and Matsushita Electric Industrial Co.[KKT]. The results show that ADENART has comparable or two/three times power of Y-MP/1, though it is very compact as a deskside machine and consumes only about several(More)
This paper presents a new parallel algorithm and performance results of iterative solution methods for three-dimensional MOSFET simulation with Gummel's method. A splitting-up operator method is proposed for incomplete factorization of sparse matrices arising from semiconductor device equations, suitable for parallel computations. This method is combined(More)
This paper presents parallel algorithm and performance in three-dimensional device simulation on a super parallel computer : ADENA (Alternating Direction Editing Nexus Array) [ 1 ], [ 2 ]. The massively parallel computation of the splitting-up CG and BCG methods is easily obtained on the ADENA computer. To realize the physical device modeling as a practical(More)
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