Tasnim Ferdous

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To meet the faster processing demand in consumer electronics, performance efficient DSP processor design is important. This paper presents a novel design and FPGA-based implementation of a 32 bit DSP processor to achieve high performance gain for reduced instruction set DSP processors. The proposed design includes a hazard-optimized pipelined architecture(More)
To satisfy the prerequisite of rapid speed signal processing design of high performance DSP processor is renowned. This paper represents a novel design and FPGA based pursuit of 64 bit DSP processor. The proposed design implicates multistage pipeline architecture and vedic algorithms to improve the speed. The DSP processor is rich with multiple application(More)
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