Taro Niiyama

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In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (V<sub>DD</sub>) for logic circuits, the dependence of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring(More)
The minimum operating voltage (VDDmin) of 90-nm CMOS ring oscillators (RO’s) is investigated in order to clarify the lower limit of supply voltage (VDD) for logic circuits. The measured VDDmin is determined by the intra-die threshold voltage random variations and increased from 91 mV to 224 mV when the number of RO stages increased from 11 to 1001, which(More)
A fine-grained body bias control to compensate both the process and design variations is proposed. A test chip was fabricated in 90nm CMOS process. The proposed global optimization scheme reduced power by 23% compared with an as-fabricated chip power and by 11% compared with the power optimized by the conventional local optimization approach. Also, the(More)
In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of the minimum operating voltage (VDD min) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90 nm CMOS ring oscillators (RO’s). The(More)
A teacher-student swap (TSS) test method with the dual supply voltage (V<sub>DD</sub>) for the ultra low V<sub>DD</sub> homogeneous multi-core LSIpsilas is proposed and the test chips are fabricated in 90 nm CMOS. In this method, two same cores with different power supply voltages test each other by comparing their outputs, which eliminates the need for the(More)
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