Tariq B. Ahmad

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The paper describes an algebraic approach to functional verification of arithmetic circuits specified at bit level. The circuit is represented as a network of half adders, full adders, and inverters, and modeled as a system of linear equations. The proof of functional correctness of the design is obtained by computing its algebraic signature using standard(More)
Traditional dynamic simulation with standard delay format (SDF) back-annotation cannot be reliably performed on large designs. The large size of SDF files makes the event-driven timing simulation extremely slow as it has to process an excessive number of events. In order to accelerate gate-level timing simulation we propose an automated fast(More)
Multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA (Electronic Design Automation) community has applied significant effort to parallelize many EDA algorithms(More)
The proliferation of multi-core hardware has led to widespread use of concurrent programs. However, these programs are notoriously difficult to get right and to debug for developers. Even for automated verification, it is a big challenge to reason about subtle synchronization between communicating threads or processes, combined with an exponential number of(More)
While multi-core computing has become pervasive, scaling single core computations to multi-core computations remains a challenge. This paper aims to accelerate RTL and functional gate-level simulation in the current multi-core computing environment. This work addresses two types of partitioning schemes for multi-core simulation: functional, and(More)
While multi-core computing has become pervasive, scaling single core computations to multi-core computations remains a challenge. This paper aims to accelerate RTL and functional gatelevel simulation in the current multi-core computing environment. This work addresses two types of partitioning schemes for multicore simulation: functional, and domain-based.(More)
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