Tapani Ahonen

Learn More
Compared to the well understood macro networks, networks-on-chip introduce novel design challenges. The characteristics of the system data flows and the knowledge of the required wire lengths can be exploited to optimize for speed and power consumption. A component library for flexible construction of interconnection architectures is being developed at the(More)
The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched network-on-chip (NoC) that applies the CDMA technique is realized in register-transfer level (RTL) using VHDL. The realized CDMA NoC supports the globally-asynchronous(More)
Network-on-Chip will be one of the cornerstones of future electronics. At Tampere University of Technology we have been working on the development of our own proposal for a flexible on-chip communication network, called Proteo. Proteo introduces the concept of an open library of communication components that can be selected and configured to build(More)
Designing accelerators for the real-time computation of Fast Fourier Transform (FFT) algorithms for state-of-the-art Orthogonal Frequency-Division Multiplexing (OFDM) demodulators has always been challenging. We have scaled-up a template-based CoarseGrain Reconfigurable Array device for faster FFT processing that generates special purpose accelerators based(More)
It is envisioned that future system-on-chip hardware platform designs will be based on reuse of a customizable processor core. Consequently, being able to quickly evaluate the key performance metrics associated with specific points in the design space becomes essential. Development of an early design phase performance estimation method for logic blocks of(More)
An FPGA prototype of a four-node globally-asynchronous locally-synchronous network-on-chip is described. The network for global communication operates asynchronously at the link level and synchronously within a node. Two C-element control pipelines constitute the control logic for the asynchronous part. C-element and asynchronous arbiter realizations on(More)
We describe a multicore Software-Defined Radio (SDR) architecture for Global Navigation Satellite System (GNSS) receiver implementation. A GNSS receiver picks up very low power signals from multiple satellites and then uses dedicated processing to demodulate and measure the exact timing of these signals from which the user’s position, velocity, and time(More)
Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related(More)
This paper describes the implementation of theW-CDMA cell search algorithm on a homogeneous general purpose Multi-Processor System-on-Chip architecture. The architecture is composed of nine nodes based on COFFEE RISC cores communicating using hierarchical Network-on-Chip. The work focuses on the parallelization of the cell search algorithm, enabling(More)
Tapani Ahonen*, Seppo Virtanen**, Juha Kylliäinen*, Dragos Truscan***, Tuukka Kasanko*, David Sigüenza-Tortosa*, Tapio Ristimäki*, Jani Paakkulainen**, Tero Nurmi**, Ilkka Saastamoinen*, Hannu Isännäinen*, Johan Lilius***, Jari Nurmi*, and Jouni Isoaho** *Institute of Digital and Computer Systems, Tampere University of Technology, Finland **Department of(More)