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This paper points to an abnormal phenomena of comparator networks. For most key processing problems (such as sorting, merging or insertion) the smaller the input size the easier the problem. Surprisingly, this is not the case for Bitonic sorting. Namely, the minimal depth of a comparator network that sorts all Bitonic sequences of n keys is not monotonic in(More)
A set of input vectors S is conclusive for a certain functionality if, for every comparator network, correct functionality for all input vectors is implied by correct functionality for all vectors in S. We consider four functionalities of comparator networks: sorting, merging, sorting of bitonic vectors, and halving. For each of these functionalities, we(More)
—Analog and Mixed Signal design flow has to be improved. In a specific application, neuromorphic engineering, we propose a definition of the analog IP (Intellectual Property) content and the structure of an IP-based library. The case study consists in the neuron-level integration of a complete system that emulates spiking neural networks. A reuse(More)
This work studies comparator networks in which several of the outputs are accelerated. That is, they are generated much faster than the other outputs, and this without hindering the other outputs. We study this acceleration in the context of merging networks and sorting networks. The paper presents a new merging technique, the Tri-section technique, that(More)
In this paper we propose a methodology for analog design reuse during technology scaling. This method is based on resizing rules resulting in the application of a MOS transistor model. The aims of this scaling are the conservation of the performances of the original circuit and the reduction of power consumption and area. This resizing methodology has been(More)