Talla Vamshi

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The Network on chip (NOC) architectures provide routing mechanism for various IP blocks in a system on chip (SOC). The existing schemes are based on the techniques are used in networking protocols similar to the conventional Ethernet communication. Such schemes suffer from data overheads and high complexity protocols. A technique based on Direct Sequence(More)
The complexity of System-On-Chip (SOC) design is increasing continuously due to the multidimensional optimization requirements, while integrating complex intellectual property (IP) blocks. The interconnectivity topologies between IPs are playing a vital role in deciding the performance of the SOCs. This paper investigates the existing code division multiple(More)
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