• Publications
  • Influence
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems
TLDR
We investigate how transactional memory can be adapted for embedded systems. Expand
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Energy efficient synchronization techniques for embedded architectures
TLDR
We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. Expand
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Energy reduction in multiprocessor systems using transactional memory
TLDR
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Expand
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Energy-Aware Microprocessor Synchronization : Transactional Memory vs . Locks
One important way in which multiprocessors differ from uniprocessors is in the need to provide programmers the ability to synchronize concurrent access to memory. Transactional memory was proposed asExpand
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SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs
TLDR
In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Expand
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Edge-TM
TLDR
We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. Expand
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A hardware/software framework for supporting transactional memory in a MPSoC environment
TLDR
We demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore, and show that it is a promising solution, even for resource-constrained embedded multiprocessors. Expand
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Speculative synchronization for coherence-free embedded NUMA architectures
TLDR
In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. Expand
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Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution
TLDR
We propose a novel scheme that allows to dynamically adjust to an evolving COP and operate at highly reduced margins, while guaranteeing forward progress. Expand
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IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM
TLDR
We propose IgnoreTM, an adaptive error management framework, that tolerates (i.e., opportunistically ignores) timing violations, allowing for more aggressive voltage scaling. Expand
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