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Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems
TLDR
We investigate how transactional memory can be adapted for embedded systems. Expand
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Energy efficient synchronization techniques for embedded architectures
TLDR
We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. Expand
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Energy reduction in multiprocessor systems using transactional memory
TLDR
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Expand
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Energy-Aware Microprocessor Synchronization : Transactional Memory vs . Locks
One important way in which multiprocessors differ from uniprocessors is in the need to provide programmers the ability to synchronize concurrent access to memory. Transactional memory was proposed asExpand
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SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs
TLDR
In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Expand
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Edge-TM
TLDR
We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. Expand
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A hardware/software framework for supporting transactional memory in a MPSoC environment
TLDR
We demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore, and show that it is a promising solution, even for resource-constrained embedded multiprocessors. Expand
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Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
TLDR
We propose a new design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of capacity and conflict evictions. Expand
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Energy Implications of Transactional Memory for Embedded Architectures
Roughly ninety percent of all microprocessorsmanufactured in any one year are intended for embedded devices such as cameras, cell-phones, or machine controllers. We evaluate the energy-efficiency andExpand
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Speculative synchronization for coherence-free embedded NUMA architectures
TLDR
In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. Expand
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