Tali Moreshet

We investigate how transactional memory can be adapted for embedded systems. Expand

We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. Expand

The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Expand

In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Expand

We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. Expand

We demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore, and show that it is a promising solution, even for resource-constrained embedded multiprocessors. Expand

We propose a new design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of capacity and conflict evictions. Expand

In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. Expand