Tali Moreshet

We investigate how transactional memory can be adapted for embedded systems. Expand

We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. Expand

The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Expand

In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP-SoCs. Expand

We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. Expand

We demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore, and show that it is a promising solution, even for resource-constrained embedded multiprocessors. Expand

In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. Expand

We propose a novel scheme that allows to dynamically adjust to an evolving COP and operate at highly reduced margins, while guaranteeing forward progress. Expand

We propose IgnoreTM, an adaptive error management framework, that tolerates (i.e., opportunistically ignores) timing violations, allowing for more aggressive voltage scaling. Expand