Takuji Sako

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Quasi-planar segmented-channel MOSFETs (SegFETs) with gate lengths down to <formula formulatype="inline"><tex Notation="TeX"> $\sim$</tex></formula>45 nm are fabricated using a conventional process flow by starting with a corrugated-silicon substrate. In comparison with control devices (fabricated using the same process flow, but with a planar-silicon(More)
To facilitate continued CMOS technology scaling, thin-body transistor structures such as the FinFET [1] and fully depleted silicon-on-insulator (FD-SOI) MOSFET [2] have been proposed to better suppress short-channel effects (SCE) than the conventional MOSFET structure in the sub-25 nm gate length (L<inf>g</inf>) regime. However, these structures require(More)
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