Taku Ohsawa

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In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures. The basic(More)
This paper presents the low power architecture and design techniques for the mobile handset LSI Medity<sup>TM</sup> M2. M2 is a second-generation mobile handset LSI which integrates a digital baseband and application processor on a chip. M2 is capable of supporting 3.2 Mbps HSDPA, WCDMA communications, and rich, high-resolution multimedia applications,(More)
We propose a speculative multi-threading processor architecture called Pinot. Pinot exploits parallelism over a wide range of granularities without modifying program sources. Since exploitation of fine-grain parallelism suffers from limits of parallelism and overhead incurred by parallelization, it is better to extract coarse-grain parallelism. Coarse-grain(More)
srfA is an operon required for the synthesis of surfactin and the development of genetic competence in Bacillus subtilis. We observed that the expression of srfA is downregulated upon treatment with H2O2. Thus, we examined the involvement of several oxidative stress-responsive transcription factors in srfA expression. Our DNA microarray analysis revealed(More)
This paper presents the low power architecture and design techniques for the mobile handset LSI Medity#8482; M2. M2 is a second-generation mobile handset LSI which integrates a Digital baseband and Application processor on a chip. M2 is capable of supporting 3.2 Mbps HSDPA, WCDMA communications, and rich, high-resolution multimedia applications, while power(More)
A one-transistor memory cell on silicon-on-insulator, called floating body cell (FBC), has been developed for high density embedded DRAM applications. The functionality of a 128Mb FBC DRAM using fully compatible 90nm CMOS technology has been successfully demonstrated. The memory cell design, such as fully-depleted (FD) operation with substrate-bias, and the(More)
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