Takeshi Ohkawa

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A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration(More)
In recent years, high-performance mobile devices such as smart phones and tablet devices spread rapidly. They have attracted attention as a new platform for parallel and distributed applications. Based on this background, we are developing a cluster computer system using wireless-connected mobile devices running Android OS. However, since mobile devices can(More)
We herein report an unusual case of apocrine carcinoma on the forehead. The lesion was formed by the anastomosis of numerous tubular structures with widespread decapitation secretion, thus demonstrating apocrine differentiation. However, we observed some unusual histopathologic features that differed from those found in typical examples of apocrine ductal(More)
Autonomous mobile robots require high-performance computation to meet variety of requirements of functions, such as sensing, intelligent image processing and controlling actuators. We focus on FPGA as a hardware platform for autonomous mobile robot system. However, a FPGA-based system is not effective in development cost, since it requires HDL-based design(More)
In recent years, robots are required to be autonomous and their robotic software are sophisticated. Robots have a problem of insufficient performance, since it cannot equip with a high-performance microprocessor due to battery-power operation. On the other hand, FPGA devices can accelerate specific functions in a robot system without increasing power(More)
A platform for networked FPGA system design, which is named "ORB Engine", is proposed to add more controllability and design productivity on FPGA-based systems composed of software and hardwired IPs. A developer can define an object-oriented interface for the circuit IP in FPGA, and implement the control sequence part using Java. The circuit IP in FPGA can(More)
Recently, multicore processors are usual in various computer systems. Thread level parallel processing is required to efficiently utilize the performance of multicore processors. To realize the automatic parallel processing that does not require program source codes, we develop a system that can parallelize sequential program binary code to the parallelized(More)
Software optimization techniques are necessary to fully utilize modern high-performance computer architectures. In development of the optimization techniques, repetitive simulations are needed to evaluate multiple candidates of optimization methods on partial code of program. Simulation of entire program codes generally takes huge amount of time. Therefore,(More)
Execution path ratio is mostly dominated by two execution paths in program loops. We have developed Two-Path Limited Speculation Method that achieves speed-up in programs using optimization of the most frequent two paths and speculative multi-thread execution of them. The path predictor used in the method predicts the next execution path in Two-Path Limited(More)
As a means for high-speed communication on the network with limited communication bandwidth such as WAN or wireless LAN environment, we can use the online high-speed data compression/decompression method. Since it is necessary to reduce the transfer time including the time of the data compression process, it is difficult to adopt the advanced but(More)