Takeshi Ohkawa

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A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration(More)
A platform for networked FPGA system design, which is named "ORB Engine", is proposed to add more controllability and design productivity on FPGA-based systems composed of software and hardwired IPs. A developer can define an object-oriented interface for the circuit IP in FPGA, and implement the control sequence part using Java. The circuit IP in FPGA can(More)
Importance of interconnection networks is continuously increasing as the number of processing elements in massively parallel computers grows. Wide spectrum of efforts in research and development for effective and practical interconnection network methods are reported, however, the problem is still open. This paper focuses discussions on congestion control,(More)
- In recent years, robots are required to be autonomous and their robotic software are sophisticated. Robots have a problem of insufficient performance, since it cannot equip with a high-performance microprocessor due to battery-power operation. On the other hand, FPGA devices can accelerate specific functions in a robot system without increasing power(More)
As a means for high-speed communication on the network with limited communication bandwidth such as WAN or wireless LAN environment, we can use the online high-speed data compression/decompression method. Since it is necessary to reduce the transfer time including the time of the data compression process, it is difficult to adopt the advanced but(More)
Recently, multicore processors are usual in various computer systems. Thread level parallel processing is required to efficiently utilize the performance of multicore processors. To realize the automatic parallel processing that does not require program source codes, we develop a system that can parallelize sequential program binary code to the parallelized(More)