Takeo Asakawa

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A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recovery mechanism is implemented for execution units(More)
We developed a 1.3-GHz SPARC-V9 processor: the SPARC64 V. This processor is designed to address requirements for enterprise servers and high-performance computing. Processing speed under multiuser interactive workloads is very sensitive to system balance because of the large number of memory requests included. From many years of experience with such(More)
We establish the existence of the top quark using a 67 pb ' data sample of pp collisions at ~s = 1.8 TeV collected with the Collider Detector at Fermilab (CDF). Employing techniques similar to those we previously published, we observe a signal consistent with tt decay to WWbb, but inconsistent with the background prediction by 4.8o.. Additional evidence for(More)
We report the results of a search for a W' boson produced in pp; collisions at a center-of-mass energy of 1.8 TeV using a 106 pb(-1) data sample recorded by the Collider Detector at Fermilab. We observe no significant excess of events above background for a W' boson decaying to a top and bottom quark pair. In a model where this boson would mediate(More)
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