Takeaki Sugimura

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A super parallel embedded processor core (MX core) for SoC (System on Chip) has been developed for multi-media application such as real-time signal processing and image processing. The developed processor realizes high processing performance, small area, low power operation and flexible programmability simultaneously. This paper describes an implementation(More)
In recent year, robust and scale invariant feature extraction algorithms such as SIFT, SURF, and U-SURF are frequently utilized for image recognition. While U-SURF[1] algorithm is robust and scalable to extract interest points and their features, it requires processes in many regions that are scattered in an image. It is difficult for the algorithm to(More)
In order to achieve human-like quick eye movements and image processing for intelligent mobile robots, a high speed vision system is developed. The vision system is composed of a binocular camera head and high speed image sensors. The camera head is originally designed to mount neuromorphic vision chips fabricated using three-dimensional integration(More)
We have proposed a new reconfigurable parallel image processing system in which three-dimensional (3D) LSI is used. A new dynamical multi-context reconfiguration scheme is employed in this system. This scheme can decrease the number of instructions between a reconfigurable processing element array and control RISC processor, and also enable efficient(More)
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