Takayoshi Owada

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We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon(More)
We have investigated the stress memorization technique (SMT) using poly-gates through both physical analysis and electrical characterization. It has been clarified that channel compressive strain in(More)