Takaya Shirasu

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A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full-NCS/duabdamascene Cu interconnects. It is emphasized that this technology is cost-effective.
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