Takashi Nakada

Learn More
Future computer systems are built under much stringent power budget due to the limitation of power delivery and cooling systems. To this end, sophisticated power management techniques are required. Power capping is a technique to limit the power consumption of a system to the predetermined level, and has been extensively studied in homogeneous systems.(More)
Oil-rich algae have promising potential for a next-generation biofuel feedstock. Pseudochoricystis ellipsoidea MBIC 11204, a novel unicellular green algal strain, accumulates a large amount of oil (lipids) in nitrogen-deficient (–N) conditions. Although the oil bodies are easily visualized by lipophilic staining in the cells, little is known about how oil(More)
This paper proposes an efficient method to analyze <i>worst case interruption delay</i> (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is(More)
This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM/MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce(More)
The evolution of oogamy from isogamy, an important biological event, can be summarized as follows: morphologically similar gametes (isogametes) differentiated into small “male” and large “female” motile gametes during anisogamy, from which immotile female gametes (eggs) evolved. The volvocine green algae represent a model lineage to study this type of sex(More)
In this paper, we proposed a light-weighted recovery scheme for fault tolerable pipeline processors after error has been detected by redundant executions. A minimal rolling back procedure is designed to schedule the re-execution based recovery in a one-cycle delay. This scheme makes full use of in-fly pipeline working status to aid the recovery, which(More)
This paper proposes a simple but efficient technique for instruction set simulators. Our simulator is made workload specific by a simple process to generate a set of C functions from a workload binary. It is as portable and retargetable as ordinary instruction emulators because the translation targets C code and works well with well-abstracted instruction(More)
Recently, many architectural level mechanisms such as dual or triple modular redundancies (DMR or TMR) have been included in high-end microprocessors to tolerate the continuously increasing electronic error rates along the process technology advancing direction. However, hardware in these space redundancy based systems is usually not well-balanced or it has(More)
Recently, reconfigurable architectures are becoming popular to achieve good energy efficiency. In this paper we designed an energy efficient, high performance accelerator, named Linear Array Pipeline Processor (LAPP). LAPP works to accelerate existing machine code executions to improve performance while maintaining the binary compatibility, instead of using(More)